In recent years, as mobile devices become widely used, battery-powered power supplies are increasingly used as a power supply for semiconductor integrated circuits such as microcomputers. When such mobile device is driven by a battery, charges of the battery are consumed with lapse of the operating time of the mobile device, and the power supply voltage of a semiconductor integrated device used decreases over a sufficiently long period of time. It is required that microcomputers do not run out of control even when the power supply voltage decreases. Based on this standpoint, reset signal generating circuits that detect a decrease in the power supply voltage and then output a reset signal are increasingly used in semiconductor integrated circuits such as microcomputers.
FIG. 3 shows a block diagram of a conventional reset signal generating circuit disclosed in Patent Document 1. In this conventional reset signal generating circuit, a comparator 12 compares a voltage Vin1, which is obtained by dividing a power supply voltage Vcc with resistors R1 and R2, and a reference voltage Vref, which is obtained from a reference voltage generating circuit 15. As soon as the power supply voltage Vcc decreases for some reason and the voltage Vin1 falls below the reference voltage, the comparator 12 turns on a switch SW0 composed of an N-channel MOS transistor to discharge charges accumulated in a capacitor C0, and a Schmitt circuit 14 outputs a low-level reset signal RES. Even after the power supply voltage Vcc is recovered, the capacitor CO is gradually charged by a constant current circuit IO, and the period during which the reset signal RES is at a low level continues until a logic threshold voltage of the Schmitt circuit 14 is exceeded. Patent Document 1 discloses that, even when the power supply voltage decreases instantaneously, system malfunctions can be avoided by generating a reset signal having a certain length.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-285046A